FT-EALU: fault-tolerant arithmetic and logic unit for critical embedded and real-time systems

This paper presents a fault-tolerant ALU (“FT-EALU”) based on time redundancy and reward/punishment-based learning approaches for real-time embedded systems that face limitations in hardware power consumption budgets. In this method, operations are diversified to three versions order correct permanent faults along with the transient ones. The diversities of considered FT-EALU provided by lightweight modifications differentiate them clear effect faults. Selecting such as shift swap would avoid high timing overhead computation while providing significant differences which necessary fault detection. Next, replicated executed serially time, their corresponding results voted derived learned weights. proposed weighted voting module generates final output module, reward/punishment strategy is employed provide weight each version execution indicating its effectiveness output. To aim, method defined execution, according correction capability confronting several faulty scenarios. Thus, defines reliability temporal well result. result generated bit computed Based scheme, positive or negative weights assigned versions. These level mitigating injection our low cost more efficient compared related research mainly information due employing static approach correcting Several experiments performed reveal efficiency capable about $$84.93\%$$ $$69.71\%$$ injected single double bits input data.